Exemplary embodiments of the present invention relate to an integrated circuit design technology, and more particularly, to a multi purpose register (MPR) of an integrated circuit.
In a system implemented with a plurality of semiconductor devices, an integrated circuit serves to store data. When a data processing device or the like (for example, a central processing unit (CPU)) requires a data input/output operation, an integrated circuit reads data from a core region that corresponds to an address inputted from the data requesting device or stores data provided from the data requesting device in, for example, a random space of a core region corresponding to the address.
Meanwhile, as the operating speed of the system implemented with semiconductor devices is becoming faster and the manufacturing technology for semiconductor integrated circuits has rapidly advanced, integrated circuits are desired to output or store data at a faster speed. Here, in order for integrated circuits to stably operate at a faster speed, circuits for providing data input/output accuracy is further provided in addition to a core region and a peripheral region for data input/output operations which are provided within integrated circuits.
Therefore, integrated circuits are to have a storage space for storing information generated by operations for obtaining the data input/output accuracy. For such storage purpose, an MPR may be used.
For example, an MPR has been used in a double data rate 3 (DDR3) synchronous dynamic random access memory (SDRAM) in order to support a read leveling operation.
The read leveling operation refers to an operation which transfers a data pattern, which is previously defined in a register within a memory chip, to a chip set and adjusts a DQS skew between the chip set and the memory chip. At this time, the operation of reading the data pattern stored in the register is performed without regard to normal data stored in a memory cell. Therefore, it is unnecessary to perform a type of a memory access operation which enables word lines or precharges bit lines in order to read data patterns.
A conventional MPR is used to store a data pattern which is not stored in a memory cell but a value of which is previously defined. Since the conventional MPR operates in such a state where it has a ‘fixed value read-out’ characteristic, an MPR rewrite operation which separately writes data is not needed. That is, if the memory chip of the semiconductor system is set to a read leveling operation mode (MPR mode), a predefined data pattern such as ‘10101010’ is outputted when a read command is inputted, without inputting an active command to the memory chip. Thus, a tuning operation (tDS/tDH) for a high speed operation between the semiconductor system and the memory chip can be performed.
However, in a memory product such as DDR4 SDRAM, a method in which a semiconductor system writes pattern data is being considered, instead of a method in which a value of pattern data is stored in and outputted from an MPR. That is, the MPR has not a ‘fixed value read-out’ characteristic but a ‘non-fixed value read-out’ characteristic.
As the characteristic of the MPR is changed, more interconnections are required in order for normal data input/output. In addition, the storage space of the MPR may increase.